Name：Gong Chen

Degrees: Ph. D.

Title：Associate Professor

Department：College of Communications & Microelectronic

Research interests：Mixed Signal IC Design, High-Speed Circuit

Research team：Sensor and Digital System Design Team

E-mail：chg@cuit.edu.cn

【Biography】

Dr. Chen Gong received his B. S. degree in in University of Electronic Science and Technology of China (UESTC) in 2005. After that, he went to study in Japan. He received his M. S. degree from the Waseda University in 2010, and the Ph.D. degree from the Kitakyushu University in 2013. Has been with Chengdu University of Information Technology since 2016.

Dr. Chen Gong has been engaged in the field of integrated circuit design, specializing in analog-digital mixed-signal design, particularly high-speed and high-precision analog-to-digital/digital-to-analog converters, power supply chips, and the design of large-scale system-on-chip. He has published over 40 papers and books on international platforms and obtained 13 patents. Dr. Chen has participated in or presided over more than ten projects, including major special projects for national defense, basic research and development projects for national defense, national natural science projects, national postdoctoral projects, and key projects of the provincial science and technology department. At the company, he presided over the design of wireless charging integrated chips and LED driver chips, such as the AP20 series, AP5889, and 6495, which have been widely used in various industrial fields including charging, adapters, and PD fast charging.

【Courses &Teaching】

Undergraduate course：Digital Integrated Circuit Design

Postgraduate course：SOPC Hardware-Software Co-design

【Projects】

(1) Sichuan Provincial Science and Technology Department, Vertical Project, 2023YFG036, Methodology for High-Performance ADC Design Based on Asynchronous Timing, January 2023 to December 2024, Funding of 200,000 yuan, Ongoing Research, Principal Investigator

(2) XX Project Management Center, Vertical Project (Confidentiality Level: Public), 2022-JCJQ-JJ-0739, Research on Key Technologies of High-Speed and High-Precision ADC, December 2022 to December 2024, Funding of 900,000 yuan, Ongoing Research, Principal Investigator

(3) XX Project Management Center, Vertical Project, XX, Theory of Noise Suppression and Channel Design Techniques for Silicon-Based Millimeter-Wave RF Front-Ends, May 2022 to May 2024, Funding of 3 million yuan, Ongoing Research, Participant

(4) Electronics Engineering Institute of China Engineering Physics Research Institute, Horizontal Project, WF18-507-12572-3, Verification of Multi-Channel Data Acquisition and Processing SoC Chip, January 2019 to July 2022, Funding of 2.87 million yuan, Completed, Principal Investigator

【Publications】

(1) Gong Chen G, Yu Zhang, Qing Dong, Mingyu Li, Shigetoshi Nakatake. Layout Dependent Effect-aware Leakage Current Reduction and Its Application to Low-power SAR-ADC. IEICE Transaction on Fundamentals of Electronics, Communication and Computer Sciences, 2015, AE98-A NO.7: 1442-1454. (Journal Article) (Note: Sole first author and corresponding author)

(2) Gong Chen G, TORU FUJIMURA, QING DONG, SHIGETOSHI NAKATAKE, BO YANG. DC Characteristics and Variability on 90nm CMOS TransistorArray-style Analog Layout. ACM Transactions on Design Automation of Electronic Systems, 2016, 21(3). (Journal Article) (Note: Sole first author and corresponding author)

(3) Yang Wenzhao, Chen Gong G. A Controllable Gain Amplifier Circuit for EEG Acquisition System. 2023 International Joint Conference on Information and Communication Engineering (JCICE 2023), Chengdu, China, May 12-14, 2023. (Conference Paper) (Note: Sole corresponding author)

(4) Tang Zhiyuan, Chen Gong G. Analog Triggered Asynchronous Clocking Technique Based on the Ring Amplifier in Pipelined ADC. 2022 IEEE 8th International Conference on Computer and Communications, Chengdu, China, December 9-12, 2022. (Conference Paper) (Note: Sole corresponding author)

(5) Huang Hong, Chen Gong G. A noise model circuit based on a high-speed pipeline ADC system. 2023 IEEE 9th International Conference on Computer and Communications (ICCC), Chengdu, China, December 8-11, 2023. (Conference Paper) (Note: Sole corresponding author)

(6) G. Chen et al., "A Linearity Bootstrapped Switch with Dynamic Bulk Biasing Design for CMOS Image Sensors," International Conference on Sensing and Imaging  (ICSI 2017), Chengdu, 2017, pp. 105-115.

(7) G. Chen et al., "A 9-bit 10MSps SAR ADC with double input range for supply voltage," 2017 IEEE 17th International Conference on Communication Technology (ICCT), Chengdu, 2017, pp. 1786-1790.

(8) G. Chen, B. Liu, S. Nakatake and B. Yang, "Routability of twisted common-centroid capacitor array under signal coupling constraints," 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), Abu Dhabi, 2016, pp. 1-4.

(9) Bo Liu, Gong Chen, Bo Yang, and Shigetoshi Nakatake. 2018. Routable and Matched Layout Styles for Analog Module Generation. ACM Trans. Des. Autom. Electron. Syst. 23, 4, Article 47 (June 2018), 17 pages.

(10) Weiwei Ling, Gong Chen, Peng Lei, Yao Yao, Li Li, Yao Huang, Hua Wei, Jiang Du, Low-firing behavior, microstructure, and electromagnetic properties of a ferroelectric-ferromagnetic composite material with multiple doping, Journal of Alloys and Compounds, Volume 750, 2018, Pages 479-489.

(11) Kun Mao, Hai Shi Wang, Yao Yao, Hai Nie, Gong Chen et al., "A 500-V High ON-BV Parasitic JFET With an Optimized Drift Region," IEEE Transactions on Electron Devices  Volume: 66, Issue: 3, March 2019

(12) Li, Li Alex, Wei Hua, Yao Yao, Gong Chen, Weiwei Ling, Jiang Du, Yao Huang, Multi-segmental OFDM signals equalization with piecewise linear channel model over rapidly time-varying channels, EURASIP Journal on Wireless Communications and Networking, 2017, Article number: 191.

(13) Juan Zhou, Ying Shen, Gong Chen, "Analysis of RF Channel Isolation Impact in Wireless Co-Time Co-Frequency Full Duplex," 2017 IEEE 17th International Conference on Communication Technology (ICCT), Chengdu, 2017, pp. 131-139.

(14) Yu Zhang, Gong Chen, Bo Yang, Jing Li, Qing Dong, Ming-Yu Li,SHIGETOSHI Nakatake . Analog Circuit Synthesis with Constraint Generation of Layout Dependent Effects by Geometric Programming. IEICE Transaction on Fundamentals of Electronics, Communication and Computer Sciences，Dec., 2013.（SCI）

(15) Ming-Yu Li, Chuan Li, Gong Chen, Yu Zhang, Qing Dong, SHIGETOSHI Nakatake. A New Sparse Design Framework for Broadband Power Amplifier Behavioral Modeling and Digital Predistortion. IEEJ Trans Elec Electron Eng, June, 2014（SCI）

(16) Gong Chen, Bo Yang, Shigetoshi Nakatake, Zhangcai Huang, Yasuaki Inoue. A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model.Circuits and Systems (ISCAS)，May，2012

(17) Gong Chen, Zhang Yu, Bo Yang, Qing Dong, Shigetoshi Nakatake. A comparator energy model considering shallow trench isolation stress by geometric programming. Quality Electronic Design (ISQED)， March，2013

(18) Gong Chen, Bo Yang, Yu Zhang, Qing Dong, Shigetoshi Nakatake. A 9-bit 50MSps SAR ADC with Pre-charge VCM –based Double Input Range Algorithm. Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI，May，2013

(19) Gong Chen, Qing Dong, Shigetoshi Nakatake, Zhangcai Huang, Yasuaki Inoue. A Novel Retargeting Methodology in Computer Aided Design of Nano-watt CMOS Reference Circuit based on Advanced Compact MOSFET Model. Journal of Computational Information Systems, March, 2015（EI）

(20) Yu Zhang, Gong Chen, Qing Dong, Ming-Yu Li, Shigetoshi Nakatake. Performance-driven SRAM macro design with parameterized cell considering layout-dependent effects, Very Large Scale Integration (VLSI-SoC), Non., 2013

(21) Qing Dong, Bo Yang, Gong Chen, Jing Li, Shigetoshi Nakatake. Transistor channel decomposition for structured analog layout, manufacturability and low-power applications. Quality Electronic Design (ISQED)， March，2012

(22) 陳功, 陰徳龍, 楊波, 董青, 李静, 中武繁寿.CMOSナノワットBGR回路のプロセス移行の制約再利用に関する考察, 電子情報通信学会技術研究報告.VLD, VLSI設計技術. March，2011

(23) 陳功, 張宇, 楊波, 董青, 中武繁寿. GP最適化法に基づくSTI制約を考慮したコンパレータ回路エネルギーモデルの提案,電子情報通信学会技術研究報告. VLD, VLSI設計技術. Aug. 2012

(24) 陳功, 張宇, 楊波, 董青, 李明玉, 中武繁寿.リーク電流抑制を伴う低電力設計方式による9bit, 20MS/s SAR ADC設計.電子情報通信学会技術研究報告.VLD, VLSI設計技術. Non. 2013

(25) Gong Chen, Zhang Yu, Mingyu Li, Qing Dong, Shigetoshi Nakatake. A Linearity Bootstrapped Switch with Dynamic Bulk Biasing Design. 第26回 回路とシステムワークショップ, July. 2013

(26) Ming-Yu Li, Gong Chen, Yu Zhang, Qing Dong, SHIGETOSHI Nakatake. Simplified Compressed Sensing-Based Volterra Model for Broadband Wireless Power Amplifiers，第26回 回路とシステムワークショップ, July. 2013

(27) 陳功, 張宇, 楊波, 董青, 李静, 中武繁寿. A 9-bit 10MSps SAR ADC with Double Input Range for Supply Voltage,電子情報通信学会技術研究報告. VLD, VLSI設計技術, Non. 2011

(28) 陳功, 陰徳龍, 楊波, 董青, 李静, 中武繁寿. CMOS Op-amp Circuit Synthesis with Geometric Programming Models for Layout-Dependent Effects,電子情報通信学会技術研究報告. VLD, VLSI設計技術, Sep. 2012

【Patents】

(1) Chen Gong, Lian Yuexing, Xiao Lan, Dong Qianyu, Ling Weiwei, Zeng Qinglin, Xie Peng. A Successive Approximation Type Capacitance Detection Circuit. Filed on June 29, 2021, China, Patent Application No. CN202110727143.2 (Patent)

(2) Chen Gong, Guo Han, Shi Yue, Ling Weiwei, Huang Yao, Dong Qianyu, Li Li, Wei Hua. A Fully Differential Amplifier for Pipelined ADC. Filed on May 8, 2020, China, Patent Application No. CN202010382472.3 (Patent)

(3) Chen Gong, Guo Han, Zeng Xue, Li Hao, Zhang Tao, Ling Weiwei, Shi Yue, Li Li, Dong Qianyu. A Self-Calibration Composite Structure ADC. Filed on June 16, 2020, China, Patent Application No. CN202010547025.9 (Patent)

(4) Chen Gong, Lian Yuexing, Gao Yuzhu, Ling Weiwei, Li Li, Dong Qianyu. An Analog Front-End Structure with Integrated Programmable Gain Amplification Function. Filed on November 25, 2019, China, Patent Application No. CN201911167715.5 (Patent)

(5) Chen Gong, Lian Yuexing, Xiao Nan, Li Hao, Zhang Tao, Wei Hua, Xu Yi, Li Li, Dong Qianyu. A Current Comparison Circuit for Overvoltage Protection. Filed on June 16, 2020, China, Patent Application No. CN202010547955.4 (Patent)

(6) Chen Gong, Guo Han, Zeng Qinglin, Xie Peng, Li Li, Dong Qianyu. A Self-Calibration Pipelined ADC. Filed on May 11, 2021, China, Patent Application No. CN202110509817.1 (Patent)

(7) Chen Gong, Yang Wenzhao, Chen Tao, Wang Xixi, Chu Haoran, Shi Yue, Li Li, Huang Yao, Ling Weiwei, Dong Qianyu. An Analog Front-End Circuit for EEG Acquisition Using Dual-Channel Multiplexing Technology. Filed on November 16, 2023, China, Patent Application No. CN202311525053.0 (Patent)

(8) Chen Gong, Tang Zhiyuan, Huang Hong, Yang Wenzhao, Zhang Jie, Shi Yue, Ling Weiwei, Dong Qianyu. An Analog Trigger Asynchronous Timing Circuit Based on Differential Output of a Ring Amplifier. Filed on June 20, 2023, China, Patent Application No. CN202310329600.1 (Patent)

(9) Chen Gong, Tang Zhiyuan, Huang Hong, Chen Tao, Chu Haoran, Yang Wenzhao, Ling Weiwei, Shi Yue, Dong Qianyu. A 4-Channel Time-Interleaved ADC Circuit Based on a Ring Amplifier. Filed on September 18, 2023, China, Patent Application No. CN202311199878.8 (Patent)

【Awards】

Dr. Chen Gong was awarded the Rongpiao Talent in 2018, the Emei Scholar in 2019, the Outstanding Judge of the National EDA Skills Competition in 2022, and invited to deliver the keynote speech at the ICCC in 2023.